1. Field of the Invention
The present invention relates to a demodulator, a demodulation method and a digital circuit for digital communication and, more particularly, to a digital communication demodulator, a digital communication demodulation method and a digital demodulation circuit designed so as to reduce the load on a central processing unit.
2. Description of the Related Art
FIG. 5 shows the configuration of a conventional receiver for receiving broadcasts via a broadcasting satellite. An antenna 1 receives electric waves from the broadcasting satellite (not shown) and outputs received signals to a converter 2. The converter 2 converts the signals from the antenna 1 into signals having predetermined lower frequencies, and outputs the converted signals to a tuner 3. The tuner 3 is controlled by a host central processing unit (CPU) 8 and receives a signal in a predetermined frequency band from the signals supplied from the converter 2, and outputs the baseband signal of the received signal to a digital demodulation circuit 4. The digital demodulation circuit 4 demodulates the baseband signal input from the tuner 3 in a digital demodulation manner (quadrature phase-shift keying (QPSK) manner) and outputs the demodulated signal to an error correction circuit 5.
The error correction circuit 5 corrects errors in the demodulated digital signal supplied from the digital demodulation circuit 4 by Viterbi decoding, reed solomon decoding or the like and outputs the corrected signal to a transport circuit 6. The transport circuit 6 separates groups of audio data and image data each formed as an independent packet, descrambles the scrambled video data and thereafter outputs the data to a Moving Picture Coding Experts Group (MPEG) decoder 7. The MPEG decoder 7 decodes each of the video data and the audio data encoded by the MPEG system on the broadcasting side, and outputs the decoded data.
The host CPU 8 controls each component according to commands from an input section 9 having switches provided on a front panel of the receiver. The host CPU 8 controls the digital demodulation circuit 4, the error correction circuit 5, the transport circuit 6 and the MPEG decoder 7 through an 8-bit bus by using control signals in a CPU format, which includes a read/write signal, a chip select signal and an address signal.
The tuner 3 is formed of a PLL synthesizer tuner and is controlled with control signals in a three-wire format. In the three-wire format, serial clock, serial data and an enable signal are used. Therefore, the host CPU 8 also generates control signals in the three-wire format other than control signals in the CPU format.
The clock rate with respect to the three-wire format for control of the tuner 3 by the host CPU 8 is a low frequency not higher than the MHz order. Therefore, when the host CPU 8 is controlling the tuner 3 so that the tuner 3 receives a signal in a predetermined frequency hand, it is occupied exclusively in the control of the tuner 3 and cannot control the other circuits.